`timescale 10ns/10ns
module mltring_t_mltring_v_tf();


// DATE:     17:26:03 09/19/2006 
// MODULE:   mltring
// DESIGN:   mltring
// FILENAME: t_mltring.v
// PROJECT:  spart
// VERSION:  


// Inputs
    reg clk;
    reg reset_b;
    reg RxD;
    reg [1:0] dipsw;


// Outputs
    wire TxD;
    wire rceb;
    wire lceb;


// Bidirs


// Instantiate the UUT
    mltring uut (
        .clk(clk), 
        .reset_b(reset_b), 
        .RxD(RxD), 
        .TxD(TxD), 
        .rceb(rceb), 
        .lceb(lceb), 
        .dipsw(dipsw)
        );


//integer - for loop
integer i;
integer j;
reg [7:0] dataBuffer [7:0];


// Initialize Inputs

        initial begin
		for(i = 0; i < 8; i = i + 1) begin
			dataBuffer[i] = 8'd97 + i;		//'a' + i
		end


		  $monitor("TxD: %b", TxD);

            clk = 0;
            reset_b = 0;
            RxD = 1;
            dipsw = 0;

		  #5
		  reset_b = 1'b0;	//reset the processor
		  dipsw = 2'b11;	//20mhz - 9600 baud

		  #5
		  reset_b = 1'b1;	//turn off reset

		  for(i = 0; i < 1; i = i + 1) begin
			
			for(j = 0; j < 10; j = j + 1) begin
				#12416 //wait 5 * 129 cycles = 1295 time units
				if(j  == 32'd0) begin
					//transmit a start bit
					RxD = 1'b0;
					$display("Sending start bit: %b", RxD);	
				end
				else if(j == 32'd9) begin
					//send a stop bit
					RxD = 1'b1;
					$display("%b", RxD);
				end
				else begin
					//send the next bit of the character array
					RxD = dataBuffer[i][j-1];
					$display("Sending stop bit: %b", RxD);
				end
			end
		  end
        end
	   always begin     //constant clock
        	clk = 0;
        	#2.5 clk = 1;
        	#2.5;
    	   end


endmodule

